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1 LTC3806 3806f synchronous flyback dc/dc controller n high efficiency at full load n better cross regulation than nonsynchronous converters (multiple outputs) n soft-start minimizes inrush current n current mode control provides excellent transient response n high maximum duty cycle: 89% typical n 2% programmable undervoltage lockout threshold n 1% internal voltage reference n micropower start-up n constant frequency operation (never audible) n 3mm 4mm 12-pin dfn package n 48v telecom supplies n 12v/42v automotive n 24v industrial n voip phone n power over ethernet the ltc ? 3806 is a current mode synchronous flyback controller that drives n-channel power mosfets and requires very few external components. it is intended for medium power applications where multiple outputs are required. synchronous rectification provides higher effi- ciency and improved output cross regulation than nonsynchronous converters. the ic contains all the necessary control circuitry includ- ing a 250khz oscillator, precision undervoltage lockout circuit with hysteresis, gate drivers for primary and syn- chronous switches, current mode control circuitry and soft-start circuitry. programmable soft-start reduces inrush currents. this makes it easier to design compliant power over ethernet supplies. low start-up current reduces power dissipation in the start-up resistor and reduces the size of the external start- up capacitor. the LTC3806 is available in a 12-pin, exposed pad dfn package. , ltc and lt are registered trademarks of linear technology corporation. sense ss g2 g1 gnd run i th fb v in intv cc LTC3806 d1 t1 c3 4.7 f c4 0.47 f c5 470 f c6 470 f 3806 f01 m1 m2 m3 v out1 3.3v 3a v out2 2.5v 3a c2 1nf c7 4.7 f c1 100 f r4 3.4k r5 0.056 r7 12.4k r6 21k r3 26.7k r8 100 r2 604k r1 51k v in 36v to 72v figure 1. multiple output flyback converter for telecom features descriptio u applicatio s u typical applicatio u
2 LTC3806 3806f 12 11 10 9 8 7 1 2 3 4 5 6 sense nc ss g1 g2 gnd run i th fb nc v in intv cc top view 13 de12 package 12-lead (4mm 3mm) plastic dfn order part number (note 1) v in voltage ............................................................. 25v intv cc voltage ......................................................... 8v intv cc output current ........................................ 50ma g1, g2 voltages ....................... C 0.3v to v intvcc + 0.3v i th , fb, ss voltages .................................C 0.3v to 2.7v run voltage ............................................... C 0.3v to 7v sense pin voltage ..................................... C 0.3v to 8v operating ambient temperature range (note 2) .................................................. C 40 c to 85 c junction temperature (note 3) ............................ 125 c storage temperature range ................. C 65 c to 125 c LTC3806ede t jmax = 125 c, q ja = 34 c/w exposed pad (pin 13) is gnd must be soldered to pcb absolute m axi m u m ratings w ww u package/order i n for m atio n w u u the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in = 10v, v run = 1.5v, unless otherwise specified. electrical characteristics consult ltc marketing for parts specified with wider operating temperature ranges. de part marking 3806 symbol parameter conditions min typ max units main control loop v in(min) minimum input voltage (note 4) 10 v i q input voltage supply current (note 5) quiescent 1000 m a shutdown mode v run = 0v 50 90 m a start-up mode v run > 1.255v, v in < 7v 80 140 m a v run + rising run input threshold voltage v in = 20v 1.205 1.230 1.255 v l 1.181 1.279 v v run C falling run input threshold voltage v in = 20v 1.116 1.139 1.162 v l 1.093 1.185 v v run(hyst) run pin input threshold hysteresis v in = 20v 45 91 137 mv i run run input current 160 na v fb feedback voltage v ith = 0.75v (note 6) 1.218 1.230 1.242 v l 1.212 1.248 v i fb feedback pin input current v ith = 0.75v (note 6) 18 100 na d v fb / d v in line regulation 10v v in 20v 0.01 %/v d v fb / d v ith load regulation v th = 0.55v to 0.95v (note 6) l C1 C0.1 % g m error amplifier transconductance i th pin load = 5 m a (note 6) 650 m mho v sense(max) maximum current sense input threshold 110 150 190 mv i sense(on) sense pin current (g1 high) v sense = 0v 35 50 m a i sense(off) sense pin current (g1 low) v sense = 1v 0.1 5 m a i ss ss pin source current v ss = 1.5v 3 5 8 m a oscillator f osc oscillator frequency 210 250 290 khz dc(max) maximum duty cycle 84 89 94 %
3 LTC3806 3806f the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in = 10v, v run = 1.5v, unless otherwise specified. electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: the LTC3806e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 34 c/w) note 4: the minimum operating voltage is allowed once operation begins. to begin operation, v in must be above the rising undervoltage lockout threshold with v run above the rising run input threshold. note 5: the dynamic input supply current is higher due to power mosfet gate charging (q g ? f osc ). see applications information. note 6: the LTC3806 is tested in a feedback loop which servos v fb to the reference voltage with the i th pin forced to a voltage between 0v and 1.4v (the no load to full load operating voltage range for the i th pin is 0.3v to 1.23v). typical perfor a ce characteristics uw fb voltage vs temperature fb voltage line regulation fb pin current vs temperature symbol parameter conditions min typ max units regulator v intvcc intv cc regulator output voltage v in = 10v 6 6.9 7.8 v d intv cc intv cc regulator line regulation 10v v in 20v 100 mv d v in v ldo(load) intv cc load regulation 0 i intvcc 20ma C6 C3 % v uvl + rising v in threshold voltage 14 15 16 v v uvl C falling v in threshold voltage 7.5 8 8.5 v gate drivers t r1 gate driver 1 output rise time c l1 = 3300pf 25 100 ns t f1 gate driver 1 output fall time c l1 = 3300pf 18 100 ns t r2 gate driver 2 output rise time c l2 = 4700pf 25 100 ns t f2 gate driver 2 output fall time c l2 = 4700pf 18 100 ns t dead gate driver dead time c l1 = 3300pf, c l2 = 4700pf 100 ns temperature ( c) ?0 fb voltage (v) 1.2400 1.2350 1.2300 1.2250 1.2200 1.2150 60 3806 g01 ?5 10 35 85 v in (v) 10 fb voltage (v) 18 3806 g02 12 14 15 20 1.2310 1.2305 1.2300 1.2295 1.2290 16 11 13 19 17 t a = 25 c temperature ( c) ?0 0 fb pin current (na) 5 10 15 20 25 30 ?5 10 35 60 3806 g03 85
4 LTC3806 3806f typical perfor a ce characteristics uw shutdown mode i q vs v in shutdown mode i q vs temperature soft-start current vs temperature g1 rise and fall time vs c l g2 rise and fall time vs c l run thresholds vs temperature frequency vs temperature v in (v) 0 shutdown mode, i q ( a) 80 70 60 50 40 30 20 10 0 16 3806 g04 4 8 12 20 14 2 6 10 18 t a = 25 c temperature ( c) ?0 50 shutdown mode, i q ( a) 55 60 65 70 75 80 ?5 10 35 60 3806 g05 85 temperature ( c) ?0 5.0 soft-start current ( a) 5.5 6.0 6.5 7.0 ?5 10 35 60 3806 g06 85 c l (pf) 0 time (ns) 150 200 250 16000 3806 g07 100 50 0 4000 8000 12000 20000 t a = 25 c c l (pf) 0 time (ns) 60 80 100 120 16000 3806 g08 40 20 0 4000 8000 12000 20000 t a = 25 c maximum sense threshold vs temperature temperature ( c) ?0 1.10 run thresholds (v) 1.12 1.14 1.16 1.18 1.20 1.22 trip ?5 10 35 60 3806 g10 85 release temperature ( c) ?0 frequency (khz) 250 255 60 3806 g11 245 240 ?5 10 35 85 260 temperature ( c) ?0 max sense threshold (mv) 151 153 155 60 3806 g12 149 147 150 152 154 148 146 145 ?5 10 35 85
5 LTC3806 3806f typical perfor a ce characteristics uw sense pin current vs temperature intv cc load regulation intv cc line regulation intv cc dropout voltage vs current, temperature temperature ( c) ?0 sense pin current ( a) 31.0 31.5 60 3806 g13 30.5 30.0 ?5 10 35 85 32.0 intv cc load (ma) 0 6.990 intv cc voltage (v) 6.995 7.000 7.005 7.010 7.015 7.020 10 20 30 40 3806 g14 50 t a = 25 c v in (v) 10 6.990 intv cc voltage (v) 6.995 7.000 7.005 7.010 7.015 7.020 12 14 16 18 3806 g15 20 intv cc load (ma) 0 1.9 dropout voltage (v) 2.0 2.2 2.3 2.4 20 40 50 2.8 3806 g16 2.1 10 30 2.5 2.6 2.7 t a = 40 c t a = 25 c t a = 55 c t a = 85 c t a = 0 c % of maximum output power 75 efficiency (%) 80 85 90 30 50 70 90 3806 g17 100 20 10 40 60 80 figure 8 circuit efficiency vs output power
6 LTC3806 3806f uu u pi fu ctio s run (pin 1): the run pin provides the user with an accurate means for sensing the input voltage and pro- gramming the start-up threshold for the converter. the falling run pin threshold is nominally 1.14v and the comparator has 91mv of hysteresis for noise immunity. when the run pin is below this input threshold, the gate drive outputs g1 and g2 are held low. the absolute maximum rating for the voltage on this pin is 7v. i th (pin 2): error amplifier compensation pin. the current comparator input threshold increases with this control voltage. nominal voltage range for this pin is 0v to 1.4v. fb (pin 3): receives the feedback voltage from the exter- nal resistor divider across the main output. nominal voltage for this pin in regulation is 1.230v. nc (pins 4, 11): do not connect. v in (pin 5): main supply pin. must be closely decoupled to ground. intv cc (pin 6): the internal 6.9v regulator output. the gate drivers and control circuits are powered from this voltage. decouple this pin locally to the ic ground with a minimum 4.7 m f low esr ceramic capacitor. gnd (pins 7, 13): ground pins. exposed pad must be tied to electrical ground. g2 (pin 8): secondary-side gate driver output. this pin drives the gates of all of the synchronous rectifiers. g1 (pin 9): primary-side gate driver output. ss (pin 10): soft-start. a capacitor between this pin and ground sets the rate at which the current comparator input threshold may increase when the ic is initially enabled. increasing the size of the capacitor slows down the ramp rate and reduces the inrush current. sense (pin 12): current sense input for the control loop. connect this pin to the current sense resistor in the source of the primary side power mosfet. internal leading edge blanking is provided.
7 LTC3806 3806f block diagra w + + 6 + regulator uv1 intv cc 5 v in 1 run 10 ss 8 g2 6.9v 3806 bd + c2 uv2 bias and start-up control soft-start slope compensation logic pwm latch current comparator run comparator intv cc v ref 1.230v v-to-i ea fb osc s r q 9 g1 intv cc + + c1 r loop i loop g m 3 gnd nc: pins 4 and 11 7 i th 2 sense 12
8 LTC3806 3806f operatio u main control loop the LTC3806 is a constant frequency, current mode flyback converter controller. a secondary-side gate driver capable of driving several mosfet synchronous rectifiers is provided. to insure best cross regulation, dc/dc con- verters using this controller operate in forced continuous conduction (current is always flowing in either the primary or secondary winding(s) of the transformer.) for circuit operation, please refer to the block diagram of the ic and figure 1. in normal operation, the primary-side power mosfet is turned on when the oscillator sets the pwm latch and is turned off when the current comparator c1 resets the latch. v out1 is divided down and compared to an internal 1.230v reference by error amplifier ea, which outputs an error signal at the i th pin. the voltage of the i th pin sets the current comparator c1 input threshold. when the load current on either output increases, a fall in the fb voltage relative to the reference voltage causes the i th pin to rise increasing the primary-side peak current thereby maintaining regulation. regulation of v out2 is indirect, occurring via transformer action. the run pin and undervoltage comparators control whether the ic is enabled or is in a low current state. with the run pin below 1.139v, the chip is off and the input supply current is typically only 50 m a. if the run pin is above 1.230v, most internal circuitry remains off until v in exceeds the undervoltage comparator uv2 threshold. this reduces start-up current to approximately 80 m a allowing smaller values for c1 and larger values for r1 to be used. the undervoltage comparator uv1 keeps g1 and g2 low until intv cc voltage is > 4.7v to insure that gate drivers will switch the external power mosfets properly. prior to normal operation, soft-start pin ss is low clamp- ing the output of the v-to-i converter to a low value causing current comparator c1 to trip at a low threshold. once operation begins, the ss pin ramps up causing the clamp voltage to rise as well. this allows progressively higher trip points on comparator c1 and progressively higher peak currents to be supplied to the primary of the trans- former. soft-start is completed when the voltage on the ss pin exceeds the voltage on the i th pin. the nominal operating frequency of the LTC3806 is 250khz. since forced continuous operation is used, the noise spectrum over all operating conditions is well controlled with virtually all noise occurring at the operating frequency and its harmonics.
9 LTC3806 3806f applicatio s i for atio wu uu intv cc regulator bypassing and operation an internal voltage regulator produces the 6.9v supply that powers the gate drivers and logic circuitry within the LTC3806. the intv cc regulator can supply up to 50ma and must be bypassed to ground immediately adjacent to the ic pins with a minimum of 4.7 m f ceramic capacitor. good bypassing is necessary to supply the high transient currents required by the mosfet gate drivers. in an actual application, most of the ic supply current is used to drive the gate capacitances of the power mosfets. as a result, high input voltage applications with large power mosfets can cause the LTC3806 to exceed its maximum junction temperature rating. the junction tem- perature can be estimated using the following equations: i q(tot) = i q + f ? q g p ic = v in ? (i q + f ? q g ) t j = t a + p ic ? r th(ja) where i q is the static supply current q g is the total gate charge of all external power mosfets p ic is the power dissipated in the ic f is the switching frequency, nominally 250khz r th(ja) is the package thermal resistance, junction to ambient, nominally 34 c/w for the 12-pin dfn package as an example, consider a 2-output power supply that uses an si7450dp primary-side power mosfet, that has a maximum total gate charge of 42nc and two si4840dy power mosfets (one for each output), each of which has 28nc maximum total gate charge. the total gate charge is: q g = 42nc + 2 ? 28nc = 98nc the total supply current is: i q(tot) = 2000 m a + 98nc ? 250khz = 27ma this demonstrates how significant the gate charge current can be when compared to static quiescent current in the ic. if v in is set to 10v, the power dissipation is: p ic = 10 ? 27ma = 270mw and the junction temperature (assuming 70 degree ambi- ent temperature) is: t j = 70 c + 270mw ? 120 c/w = 102.4 c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked when operating at high v in . if junction temperature is too high, using a separate transformer winding to lower v in may be tried. prior to adding an additional transformer winding (which raises transformer cost), be sure to check with power mosfet manufacturers for their newest low q g , low r ds(on) devices. power mosfet manufacturing tech- nologies are continually improving, with newer and better performance devices being introduced almost yearly. output voltage programming this ic will generally be used in dc/dc converters with multiple outputs. the output voltage of the master output (v out1 ) is set by a resistor divider according to the following formula: vv r r out1 1 230 1 6 7 =+ ? ? ? ? . the external resistor divider is connected as shown in figure 1. the resistors r6 and r7 are typically chosen so that the error caused by the current flowing into the fb pin during normal operation is less than 1% (this translates to a maximum value of r7 of about 120k). the nominal slave output (v out2 ) voltage is set according to the following formula: v out2 = v out1 ? n21 where n21 is the turns ratio of the transformer windings between v out2 and v out1 . if additional slave outputs are added their voltage is determined by the equation: v outn = v out1 ? n n1 where n n1 is the turns ratio of the transformer windings between v outn and v out1 .
10 LTC3806 3806f applicatio s i for atio wu uu cross regulation and tracking between the master and slave outputs are impacted by transformer and secondary-side power mosfet selection. select a power mosfet with low on resistance. in addition, a transformer with low winding resistances and highest coupling coefficient will have better cross regulation and tracking. composite feedback in applications where accuracy is important on more than one output, composite feedback may be used. this sacri- fices some of the accuracy of one output for improved accuracy on the other output(s). figure 2 shows how composite feedback can be applied to two outputs. select a value for r7 less than or equal to 120k. now choose the fraction k of the total feedback taken from v out1 . the higher the fraction used, the tighter v out1 is controlled, but the poorer v out2 is controlled (since it contributes less to the total feedback). the values for r6a and r6b can now be calculated: ra r k v v rb r k v v out ref out ref 6 7 1 6 7 1 1 1 2 = ? ? ? ? = ? ? ? ? this technique can easily be extended to more outputs if needed. programming turn-on and turn-off thresholds with the run pin the LTC3806 leaves a comparator detection circuit and the voltage reference active even when the device is shut down (figure 3). this allows users to accurately program an input voltage at which the converter will turn on and off. r7 3806 f02 r6b fb r6a out1 out2 figure 2. composite feedback + run comparator v in run r2 r1 input supply optional filter capacitor + gnd 3806 f03a bias and start-up control 1.230v reference 6v + run comparator 1.230v 3806 f03b run 6v external logic control + run comparator v in run r2 1m input supply + gnd 1.230v 3806 f03c 6v figure 3a. programming the turn-on and turn-off thresholds using the run pin figure 3b. on/off control using external logic figure 3c. external pull-up resistor on run pin for always on operation
11 LTC3806 3806f the rising threshold voltage on the run pin is equal to the internal reference voltage of 1.230v. the comparator has 91mv of hysteresis to increase noise immunity. the turn-on and turn-off input voltage thresholds are programmed using a resistor divider according to the following formulas: vv r r vv r r in off in on () () . . =+ ? ? ? ? =+ ? ? ? ? 1 139 1 2 1 1 230 1 2 1 the resistor r1 is typically chosen to be less than 1m. for applications where the run pin is only to be used as a logic input, the user should be aware of the 7v absolute maximum rating for this pin! the run pin can be connected to the input voltage through an external 1m resistor, as shown in figure 3c, for always on operation. application circuits a basic LTC3806 application circuit is shown in figure 1. external component selection is driven by the character- istics of the load and the input supply. duty cycle considerations current and voltage stress on the power switch and synchronous rectifiers, input and output capacitor rms currents and transformer utilization (size vs power) are impacted by duty factor. unfortunately duty factor cannot be adjusted to simultaneously optimize all of these re- quirements. in general, avoid extreme duty factors since this severely impacts the current stress on most of the components. a reasonable target for duty factor is 50% at nominal input voltage. using this rule of thumb, calculate the ideal transformer turns ratio: n v v d d ideal out in = ? ? ? ? 1 1 applicatio s i for atio wu uu for a 50% duty factor, this reduces to: n v v ideal out in = 1 if n ideal is integer, use this for your turns ratio. if not, find a ratio of small integers that comes close to n ideal . if these conditions are met, bifilar winding techniques can be used that will improve coupling coefficient. cross regulation will be better and primary-side snubbing may be reduced or eliminated. the selected turns ratio doesnt have to be perfectly equal to n ideal because a flyback converters output voltage is not set through transformer action. instead, the trans- former stores energy when the primary-side switch turns on and transfers this energy to the output(s) by flyback action when the primary-side switch turns off. cross regulation may be improved by using a target duty factor which is less than 50%. this improves cross regulation because the secondary-side mosfets (syn- chronous rectifiers) will be on a larger percentage of the time (thereby increasing the average coupling between the outputs). duty factor is reduced by proportionately in- creasing all turns ratios. reduced duty factor has the following effect on mosfet stresses: mosfet mosfet location current stress voltage stress primary increased reduced secondary reduced increased the duty factor with the selected turns ratio will equal: d v vnv out out in = + () 1 1 while the output(s)/input turns ratio are not critical, the turns ratio between outputs are critical and affect the accuracy of the slave output voltages.
12 LTC3806 3806f applicatio s i for atio wu uu for example, assume we need a regulator that operates with a nominal 48v input to produce one 3.3v output and one 5v output. the ideal turns ratio for the 3.3v (master) output is: n ideal1 33 48 0 06875 == . . we select a turns ratio of 1/15 or n1 = 0.066 for the 5v output, the ideal turns ratio is: nn ideal2 1 5 33 0 1010 == . . ... if we choose: n2 = 1 10 and we assume out1 is exact, the voltage on slave output 2 is: vv out2 33 1 10 1 15 33 15 495 === . .. . this does not include any other errors, so make sure that the error in v out2 is only a fraction of what your specifica- tion allows. when dealing with large numbers of outputs trial and error is usually required to get reasonable turns ratios on all outputs while keeping the errors (due to imperfect turns ratios) low. for the selected turns ratios, the duty factor for this design with 48v input would be: d v vnv v v v out out in = + () = + ? ? ? ? = 1 1 33 33 48 15 0 508 . . . input power the maximum input power is: p p eff in outk k n = ? = 1 where p outk is the maximum power supplied by output k and eff represents the efficiency of the converter. continuing the previous example, assume out1 delivers 3.3v at 2a and out2 delivers 4.95v at 0.5a. for a conversion efficiency at maximum output power of 80%: p va v a w in = + = 33 2 495 05 080 11 34 . . . . . transformer selection the transformer primary inductance, l p , is selected based on the percentage peak-to-peak ripple current (x) in the transformer relative to its maximum value. in general, x should range from 20% to 40% ripple current (i.e., x = 0.2 to 0.4). higher values of ripple will increase conduction losses, while lower values will require larger cores. ripple current and percentage ripple will be largest at minimum duty factor d, in other words at the highest input voltage. l p can be calculated from: l vd fx p p in max min max in = () 22 where f is nominally 250khz. continuing the example, allow 40% maximum ripple at a maximum input voltage of 72v: d v v v l v hz w h min p = + = ==m 33 33 72 15 0 407 72 0 407 250000 0 4 11 34 757 22 . . . . . . some common secondary turns ratios: v out turns 2.5 3 3.3 4 3.3 2 5.0 3 1.8 6 3.3 11 1.8 5 2.5 7 2.5 3 3.3 4 5.0 6
13 LTC3806 3806f for a minimum input voltage of 36v, the largest duty factor is: d v v v max = + = 33 33 36 15 0 579 . . . and the minimum percentage ripple is: x vd fl p v khz h w min in max pin = = m = 22 22 36 0 579 250 757 11 34 20 2 . . .% transformer core selection once l p is known, the type of transformer must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite cores. actual core loss is inde- pendent of core size for a fixed inductance, but is very dependent on the inductance selected. as inductance in- creases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore cop- per losses will increase. generally, there is a tradeoff be- tween core losses and copper losses that needs to be balanced. in addition, increased winding resistance will degrade cross regulation. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can con- centrate on copper losses and preventing saturation. ferrite core material saturates hard, meaning that the inductance collapses rapidly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequently, output voltage ripple. do not allow the core to saturate! the maximum peak primary current occurs at minimum v in : i p vd x pk in in min max min =+ ? ? ? ? () 1 2 current sense resistor selection the control circuit limits the maximum voltage drop across the sense resistor to about 120mv (at low duty cycle), and only about 70mv at a duty cycle of 92% due to slope compensation. use figure 4 and d max to determine the maximum allowable drop in the sense resistor. using this value calculate: r v i sense drop pk applicatio s i for atio wu uu duty cycle 0 maximum current sense voltage (mv) 100 150 0.8 3806 f04 50 0 0.2 0.4 0.5 1.0 200 t a = 25 c figure 4. maximum sense threshold voltage vs duty cycle capacitor selection in a flyback converter, the input and output current flows in pulses placing severe demands on the input and output filter capacitors. the input and output filter capacitors should be selected based on rms current ratings and ripple voltage. select an input capacitor with a ripple current rating greater than: i p v d d rms in in min max max = () 1 continuing the example: i w v a rms rms == 11 34 36 1 0 579 0 579 0 269 .. . . low effective series resistance and inductance is also important in the input capacitor since it affects the electro- magnetic interference suppression. in some instances high esr can also produce stability problems because flyback converters exhibit a negative input resistance
14 LTC3806 3806f characteristic. refer to application note 19 for more information. the output capacitor is sized to handle the ripple current and to insure acceptable output voltage ripple. the output capacitor should have a ripple current rating greater than: ii d d rms out max max = 1 this should be calculated for each output. for our ex- ample, the out1 capacitor needs an rms current rating greater than: ia a rms rms == 2 0 579 1 0 579 235 . . . the out2 capacitor rms current rating is calculated in a similar manner. the capacitor rating should be greater than 586ma rms . one final note, most capacitor manufac- turers base their ripple current ratings on only 2000 hours life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. contributions of esr (equivalent series resistance), esl (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct compo- nent for a given output ripple voltage. the effects of these three parameters (esr, esl and bulk c) on the output voltage ripple waveform are illustrated in figure 5 for a typical flyback converter. the capacitance calculation begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the esr step and the charging/discharging d v. for the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the esr step and the charging/discharging d v. this percent- age ripple will change, depending on the requirements of the application, and the equations provided below can easily be modified. for a 1% contribution to the total ripple voltage, the esr of the output capacitor can be determined using the following equation: esr vd i cout out max out () 001 1 . for the bulk c component, which also contributes 1% to the total ripple: c i vf out out out 3 001 . for many designs it is possible to choose a single capaci- tor type that satisfies both the esr and bulk c require- ments for the design. in certain demanding applications, however, the ripple voltage can be improved significantly by connecting two or more types of capacitors in parallel. for example, using a low esr ceramic capacitor can minimize the esr step, while an electrolytic capacitor can be used to supply the required bulk c. applicatio s i for atio wu uu output voltage ripple waveform secondary current primary current i pri ? v cout 3806 f05 ringing due to esl i pri n ? v esr figure 5. typical flyback converter waveforms (single output)
15 LTC3806 3806f applicatio s i for atio wu uu continuing our previous example the filter capacitor for output 1 needs: esr v a m c a v khz f cout out () =w 3=m 001 33 1 0579 2 7 2 0 01 3 3 250 242 .. . .. to get an electrolytic capcitor with an esr this low would require c out much larger than 242 m f. combining a low esr ceramic capacitor in parallel with an electrolytic capacitor provides better filtering at lower cost. for output 2, the output capacitor needs an esr less than 42m w and a bulk c greater than 40.4 m f. this can be achieved with a single high performance capacitor such as a sanyo os-con or equivalent. once the output capacitor esr and bulk capacitance have been determined, the overall ripple voltage waveform should be verified on a dedicated pc board. parasitic inductance from poor layout can have a significant impact on ripple. refer to the layout section for details. power mosfet selection important selection criteria for the power mosfets in- clude the on resistance r ds(on) , input capacitance, drain-to-source breakdown voltage (bv dss ) and maxi- mum drain current (i d(max) ). narrow the choices for power mosfets by first looking at the maximum drain currents. for the primary-side power mosfet: i p vd x pk in in min max min =+ ? ? ? ? () 1 2 for each secondary-side power mosfet: i i d x pk out max min =+ ? ? ? ? 1 1 2 from the remaining mosfet choices, narrow the field based on bv dss . select a primary-side power mosfet with a bv dss greater than: bv i l c v v n dss pk lkg p in max out max 3++ () () where l lkg is the primary-side leakage inductance and c p is the primary-side capacitance (mostly from the c oss of the primary-side power mosfet). a snubber may be added to reduce the leakage inductance related spike. for more information on snubber design, refer to application note 19. for each secondary-side power mosfet, the bv dss should be greater than: bv dss 3 v out + v in(max) ? n next, select a logic-level mosfet with acceptable r ds(on) at the nominal gate drive voltage (usually 6.9vset by the intv cc regulator). calculate the required rms currents next. for the primary- side power mosfet: i p vd rmspri in in min max = () for each secondary-side power mosfet: i i d rmssec out max = - 1 calculate mosfet power dissipation next. because the primary-side power mosfet operates at high v ds , a term for transition power loss must be included in order to get an accurate fix on power dissipation. c miller is the most critical parameter in determining the transition loss but is not directly specified on mosfet data sheets. c miller can be calculated from the gate charge curve in- cluded on most data sheets (figure 6). the curve is gen- erated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. the initial slope is the result of the gate-to-source and the gate-to-drain capaci- tance. the flat portion of the curve is the result of the miller (gate-to-drain) capacitance as the drain voltage drops. the upper sloping line is due to the gate-to-drain accumulation capacitance and the gate-to-source capacitance. the miller
16 LTC3806 3806f charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given v ds , but can be adjusted for different v ds voltages by multiplying by the ratio of the application v ds to the curve specified v ds values. to estimate the c miller term, take the change in gate charge from points a and b on the manufacturers data sheet and divide by the specified v ds . with c miller determined, calculate the primary-side power mosfet power dissipation: pi r v p d rc vv f dpri rmspri ds on in max in max min dr miller intvcc th =+ () + ? ? ? ? 2 1 1 () ( ) () d where r dr is the gate1 driver resistance (maximum is approximately 6 w ), v th is the typical gate threshold volt- age for the specified power mosfet and f is the operating frequency, typically 250khz. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/ c can be used as an approximation for low voltage mosfets. the secondary-side power mosfets typically operate at substantially lower v ds , so transition losses can be ne- glected. the dissipation may be calculated using: p dsec = i rmssec 2 ? r ds(on) (1 + d ) for a known power dissipation in the power mosfets, the junction temperatures can be obtained from the equation: t j = t a + p d ? r th(ja) where t a is the ambient temperature and r th(ja) is the mosfet thermal resistance from junction to ambient. compare t j against your initial estimate for t j and if necessary, recompute d , power dissipations and t j . iter- ate as necessary. selecting the compensation network load step testing can be used to empirically determine compensation. application note 25 provides information on the technique. when the regulator has multiple out- puts, compensation should be optimized for the master output. pc board layout checklist 1. in order to minimize switching noise and improve out- put load regulation, the gnd pin of the LTC3806 should be connected directly to 1) the negative terminal of the intv cc decoupling capacitor, 2) the negative terminal of the output decoupling capacitors, 3) the bottom ter- minal of the current sense resistor, 4) the negative ter- minal of the input capacitor and 5) at least one via to the ground plane immediately adjacent to pin 6 (gnd). 2. beware of ground loops in multiple layer pc boards. try to maintain one central ground node on the board and use the input capacitor to avoid excess input ripple for high output current power supplies. if the ground plane is to be used for high dc currents, choose a path away from the small-signal components. 3. place the c vcc capacitor immediately adjacent to the intv cc and gnd pins on the ic package. this capacitor carries high di/dt mosfet gate drive currents. a low esr x5r 4.7 m f ceramic capacitor works well here. 4. the high di/dt loop from the bottom terminal of the input capacitor through the sense resistor, primary- side power mosfet, transformer primary and back through the input capacitor should be kept as tight as possible in order to reduce emi. also keep the loops formed by the outputs as tight as possible. 5. check the switching waveforms of the mosfets using the actual pc board layout. measure directly across the power mosfet terminals to verify that the bv dss specification of the mosfet is not exceeded due to inductive ringing. if this ringing cannot be avoided and applicatio s i for atio wu uu miller effect a v gs q in c miller = (q b ?q a )/v ds b v in @ v ds device under test i gate 3806 f06 v gs + figure 6. gate charge curve and test circuit
17 LTC3806 3806f exceeds the maximum rating of the device, either choose a higher voltage device or specify an avalanche-rated power mosfet. 6. place the small-signal components away from high frequency switching nodes. (all of the small-signal components on one side of the ic and all of the power components on the other.) this allows the use of a pseudo-kelvin connection for the signal ground, where high di/dt gate driver currents flow out of the ic ground pin in one direction (to the bottom plate of the intv cc decoupling capacitor) and small-signal currents flow in the other direction. 7. minimize the capacitance between the sense pin trace and any high frequency switching nodes. the LTC3806 contains an internal leading edge blanking time of approximately 180ns, which should be adequate for most applications. applicatio s i for atio wu uu 8. for optimum load regulation and true remote sensing, the top of the output resistor divider should connect independently to the top of the the output capacitor (kelvin connection), staying away from any high dv/dt traces. place the divider resistors near the LTC3806 in order to keep the high impedance fb node short. 9. for applications with multiple switching power convert- ers which connect to the same input supply, make sure that the input filter capacitor for the LTC3806 is not shared with other converters. ac input current from another converter could cause substantial input voltage ripple and this could interfere with the operation of the LTC3806. a few inches of pc trace or wire (l @ 100nh) between the c in of the LTC3806 and the actual source v in should be sufficient to prevent current sharing problems. figure 7. synchronous flyback sense nc ss g1 g2 gnd 1 2 3 4 5 6 12 11 10 9 8 7 run i th fb nc v in intv cc LTC3806 r9 33k r10 12.4k c14 1nf c16 100pf c20 4.7 f d4 20v c19 220nf c15 220nf r16 76.8k r17 12.4k r13 42.3k r5 232k r4 47k r1 22 c5 2.2 f d1 1n4148 v in 25v to 60v r3 tbd 11 2 1 12 7 6 10 3 8 5 9 4 c18 100 f r14 0.056 q4 si4490dy q1 si7806dn q5 si7806dn t1 xfmr_efd20 q2 si7806dn c25 100nf d8 10v r18 100k c1 1nf r2 10 d2 b260a c7 220pf c6 100 f 5v 1.5a 3.3v 2a c26 100 f 3806 f07 ?v 1.5a c2 10 f 12v 400ma c8 470 f poscap +
18 LTC3806 3806f table 1. recommended component manufacturers vendor components telephone web address avx capacitors 207-282-5111 avxcorp.com bh electronics transformers 952-894-9590 bhelectronics.com coiltronics transformers 407-241-7876 coiltronics.com diodes, inc. diodes 805-446-4800 diodes.com fairchild mosfets 408-822-2126 fairchildsemi.com general semiconductor diodes 516-847-3000 gerneralsemiconductor.com international rectifier mosfets, diodes 310-322-3331 irf.com irc sense resistors 361-992-7900 irctt.com kemet tantalum capacitors 408-986-0424 kemet.com magnetics inc. toroid cores 800-245-3984 mag-inc.com microsemi diodes 617-926-0404 microsemi.com murata-erie capacitors 770-436-1300 murata.co.jp nichicon capacitors 847-843-7500 nichicon.com on semiconductor diodes 602-244-6600 onsemi.com panasonic capacitors 714-373-7334 panasonic.com sanyo capacitors 619-661-6835 sanyo.co.jp taiyo yuden capacitors 408-573-4150 t-yuden.com tdk capacitors, transformers 562-596-1212 component.tdk.com thermalloy heat sinks 972-243-4321 aavidthermalloy.com tokin capacitors 408-432-8020 tokin.com united chemicon capacitors 847-696-2000 chemi-com.com vishay/dale resistors 605-665-9301 vishay.com vishay/siliconix mosfets 800-554-5565 vishay.com vishay/sprague capacitors 207-324-4140 vishay.com zetex small-signal discretes 631-543-7100 zetex.com applicatio s i for atio wu uu nc sense ss g2 g1 gnd nc run i th fb v in intv cc 12 11 10 9 8 7 1 2 3 4 5 6 LTC3806 d1 1n4148 c3 4.7 f c6 100pf c5 100 f c7 1nf d2 20v c8 470nf q1 si7450dp q2 si7358dp q3 si7448dp c4 330pf c1 1.5 f c2 330 f l1 4.7 h t1 pulse pa0031 3806 ta01 v out 3.3v 8a r1 220 r10 12.5k r9 3.3k r6 51k r7 12.5k r5 330k v in 36v to 72v r8 20.5k r11 100 r2 0.1 typical applicatio u synchronous forward application
19 LTC3806 3806f u package descriptio ue/de package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695) 4.00 0.10 (2 sides) 3.00 0.10 (2 sides) note: 1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom view?xposed pad 1.70 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 0.25 0.05 3.30 0.10 (2 sides) 1 6 12 7 0.50 bsc pin 1 notch pin 1 top mark (note 6) 0.200 ref 0.00 ?0.05 (ue12/de12) dfn 0603 0.25 0.05 3.30 0.05 (2 sides) recommended solder pad pitch and dimensions 1.70 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20 LTC3806 3806f ? linear technology corporation 2004 lt/tp 0104 1k ? printed in the usa part number description comments lt ? 1619 current mode pwm controller 300khz fixed frequency, boost, sepic flyback topology ltc1624 current mode dc/dc controller so-8; 300khz operating frequency; buck, boost, sepic design; v in up to 36v ltc1700 no r sense tm synchronous step-up controller up to 95% efficiency, operation as low as 0.9v input lt1725 general purpose isolated flyback controller drives external power mosfet, senses output voltage directly from primary side switchingno optoisolator required, 16-pin ssop ltc1871 wide input range current mode no r sense controller 50khz to 1000khz frequency; boost, flyback and sepic topology ltc1872 sot-23 boost controller delivers up to 5a, 550khz fixed frequency, current mode lt1910 protected high side mosfet driver 8v to 48v power supply range; protected from C15v to 60v supply transients, short-circuit protection, automatic restart timer lt1930 1.2mhz sot-23 boost converter up to 34v output, 2.6v v in 16v, miniature design lt1931 inverting 1.2mhz, sot-23 converter positive-to-negative dc/dc conversion, miniature design lt1950 single switch forward controller 3v v in 25v, 25w to 500w, programmable slope compensation ltc3401/ltc3402 1a/2a, 3mhz synchronous boost converters up to 97% efficiency, very small solution, 0.5v v in 5v lt3781/ltc1698 36v to 72v input isolated dc/dc converter chipset synchronous operation; overvoltage/undervoltage protection; 10w to 100w power supply; 1/2-, 1/4-brick footprint ltc3803 sot-23 flyback contoller adjustable slope compensation, internal soft-start, 200khz no r sense is a trademark of linear technology corporation. related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com typical applicatio u figure 8. mulitple output flyback converter for telecom sense nc ss g2 g1 gnd 1 2 3 4 5 6 12 11 10 9 8 7 run i th fb nc v in intv cc LTC3806 r4 33k 0603 r3 12.4k 0603 c8 1nf 0603 c9 100pf 0603 c12 220nf 0603 r5 0.033 1206 q1 si4490 q2 si7806dn gnd 13 fb c15 4.7 f 10v 0805 + r6 12.4k 0603 r7 20.5k 0603 q3 si7806dn q4 si7806dn c10 470 f 4v poscap 7343 c11 100 f 1210 v out 2.5v 2a 3 5 4 9 8 10 6 11 1 2 12 7 t1 xfmr efd20 d2 1a 60v b260a sma + c6 470 f 4v poscap 7343 c7 100 f 1210 c5 47 f 1812 c4 10 f 1812 v out 3.3v 3a gnd 3806 f08 v out 5v 400ma v out 12v 400ma gnd r2 47k 0805 r1 232k 0805 + c13 100 f 35v tant 7343 d3 20v 225mw c14 220nf 0603 c3 2.2 f 100v 1812 c2 220nf 1206 c1 10 f 63v elec d1 1n4148w sod123 l1 3.3 h + v in 25v to 60v gnd

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